This application relates in general to digital processing and more specifically to a digital processor microarchitecture for reducing power consumption in processors.
Reducing power consumption in microprocessor design is becoming more important as increasing numbers of portable digital processing applications, such as cellular telephones, personal digital assistants (PDAs), pocketbook computers, etc., become more popular. Also, as digital processors become faster, and as process technologies allow for increasingly dense designs, the effective capacitance, Ceff, encountered in new processor designs increases. The increased Ceff can require prohibitive amounts of power to achieve desired speeds. Recent projections indicate that traditional processor architectures that include significant random-access memory (RAM) and read-only memory (ROM) in the processor's microstore, cache, buffers, registers and other areas; requires much more power due to fast signal switching requirements encumbered by high Ceff.
Traditionally, the liberal use of memory at the processor level has been desirable. The program store allows the processor to be re-configured with updated instruction set functionality. The design of microprocessor instructions, or the “instruction set,” can be changed to a degree without greatly affecting hardware design. The use of a microinstruction cache allows instructions that need to be repeated many times to be more quickly accessed by placing instructions within the loop to be executed in the fast cache. However, the use of large memories and memory caches also require cell arrays, control lines, decode logic, etc., whose operations are highly affected by Ceff. In general, storage accessing has a significant overhead at speeds desired for central processing unit (CPU) instruction execution.
The prior art has tried to minimize the use of memory devices in modem processor architecture designs by making the microinstruction or instruction cache extremely small, and by using large, complex instructions, e.g., very long instruction word (VLIW) or complex instruction set computer (CISC) approaches. These approaches use large instruction words, that can perform one or more functions that would otherwise require multiple, simpler, instructions. At an extreme, a single complex microinstruction might be the entirety of a loop so that frequently-executed loops and functions can be performed by keeping the single microinstruction in a small, single-word cache and executing the same microinstruction many times. However, the mere operation of looping a register, memory or cache, requires high switching speeds of signals in many transistors in the register memory, control memory and associated support circuitry. Such an approach is prohibitive where Ceff is large. The trend of denser numbers of transistors to control more and more circuitry and chip designs is causing a rapid increase in Ceff. Other aspects of microprocessor design can further thwart register and memory oriented approaches.
Thus, it is desirable to provide a system that alleviates one or more shortcomings in the prior art.